久久久国产一区二区三区四区小说_久久久黄色大片_久久久极品_久久久经典_一级久久_一级久久久久

岗位职责:1. RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.2. Design flow/methodology development and innovation for front-end design challenges.3. Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips. 任职资格:1. MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.2. New graduate or 3 years working experience.3. Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.4. Familiar with tcl/Perl/Python program. 职能类别：半导体技术 关键字：芯片设计